The ADATA's module is a 1024Mx72 bits 8GB(8192MB) DDR3-1600(CL11)-11-11-28 SDRAM memory module. The SPD is programmed to JEDEC standard latency 1600Mbps timing of 11-11-11-28 at 1.5V. The module is composed of eight-teen 512Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass-epoxy printed circuit board. The module is a Dual In-line Memory Module and intended for mounting onto 240-pins edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.